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ssram as5sp512k36 as5sp512k36 rev. 3.0 10/13 micross components r eserves the right to change products or speci cations without notice. 1 plastic encapsulated microcircuit 18mb, 512k x 36, synchronous sram pipeline burst, single cycle deselect features ?? synchronous operation in relation to the input clock ?? 2 stage registers resulting in pipeline operation ?? on chip address counter (base +3) for burst operations ?? self-timed write cycles ?? on-chip address and control registers ?? byte write support ?? global write support ?? on-chip low power mode [powerdown] via zz pin ?? interleaved or linear burst support via mode pin ?? three chip enables for ease of depth expansion without data contention. ?? two cycle load, single cycle deselect ?? asynchronous output enable (oe\) ?? three pin burst control (adsp\, adsc\, adv\) ?? 3.3v core power supply ?? 3.3v/2.5v io power supply ?? jedec standard 100 pin tqfp package ?? available in industrial , enhanced , and mil- temperature operating ranges ??????? rohs compliant options available general description the as5sp512k36 is a 18mb high performance synchronous pipeline burst sram, available in multiple temperature screening levels, fabricated using high performance cmos technology and is organized as a 512k x 36 array. it integrates address and control registers, a two (2) bit burst address counter supporting four (4) double-word transfers. writes are internally self-timed and synchronous to the rising edge of clock. the as5sp512k36 includes advanced control options including global write, byte write as well as an asynchronous output enable. burst cycle controls are handled by three (3) input pins, adv\, adsp\ and adsc\. burst operation can be initiated with either the address status processor (adsp\) or address status controller (adsc\) inputs. subsequent burst addresses are generated internally in the system?s burst sequence control block and are controlled by the address advance (adv\) control input. paramete r symbol 200mhz 166mhz 133mhz units cycle time tcyc 5.0 6.0 7.5 ns clock access time tcd 3.1 3.5 4.0 ns output enable access time toe 3.1 3.5 4.0 ns fast access times 100-pin tqfp pinout (3-chip enable) block diagram control block burst cntl. address registers row decode column decode memory array x36 sbp i/o gating and control output register input register clk ce1\ ce2 ce3\ bwe\ bwx\ gw\ adv \ adsc \ adsp\ mode a0-ax dqx, dqpx output driver ? synchronous pipeline burst ? two (2) cycle load ? one (1) cycle de-select ? one (1) cycle latency on mode change oe\ zz
ssram as5sp512k36 as5sp512k36 rev. 3.0 10/13 micross components r eserves the right to change products or speci cations without notice. 2 address register adv clk burst counter and logic clr q1 q0 adsp adsc mode bwe gw ce 1 ce 2 ce 3 oe enable register output registers sense amps output buffers e pipelined enable input registers a0, a1, a bw b bw c bw d bw a memory array dqs dqp a dqp b dqp c dqp d sleep control zz a [1:0] 2 dq a , dqp a byte write register dq b , dqp b byte write register dq c , dqp c byte write register dq d , dqp d byte write register dq a , dqp a byte write driver dq b , dqp b byte write driver dq c , dqp c byte write driver dq d ,dqp d byte write driver pin descriptions low order, synchronous address inputs and burst counter address inputs. 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50, 43, 42 chip enable ce1\, ce3\ sync input 98, 92 active low chip enables. chip enable ce2 sync input 97 active high chip enable. global write enable gw\ sync input 88 active low global write enable. write to all bits. bwa\, bwb\, bwc\, bwd\ byte write enable bwe\ sync input 87 active low byte write function enable. output enable oe\ input 86 active low asynchronous output enable. asynchronous, non-time critical power-down input control. places the chip into an ultra low power mode, with data preserved. 52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23, 24, 25, 28, 29 burst mode mode input 31 interleaved or linear burst mode control. power supply [core] vdd supply 91, 15, 41, 65 core power supply. ground [core] vss supply 90, 17, 40, 67 core power supply ground. 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76 address advance power-down dqpa, dqpb, dqpc, dqpd synchronous clock. when asserted low, address is captured in the address registers and a0- a1 are loaded into the burst counter when adsp\ and adsc\ are both asserted, only adsp\ is recognized. when asserted low, address is captured in the address registers, a0-a1 is registered in the burst counter. when both adsp\ and adsc\ or both asserted, only adsp\ is recognized. adsp\ is ignored when ce1\ is high. when asserted low, address in burst counter is incremented on rising edge of clock. synchronous parity on input/output. isolated input/output buffer ground. isolated input/output buffer supply. dqa, dqb, dqc, dqd sync input/ output sync input/ output synchronous data input/output. no connection(s) nc na no connections to internal silicon. 14, 16, 38, 39, 66 data input/outputs supply supply vddq vssq i/o ground clk input 89 37, 36 clock 93, 94, 95, 96 active low byte write enables. write to byte segments. byte enables address address a0, a1 a synchronous address inputs power supply i/o address status processor address status controller adsc\ 85 84 adsp\ sync input sync input 83 adv\ zz input 64 51, 80, 1, 30 data parity input/outputs sync input sync input(s) sync input sync input logic block diagram
ssram as5sp512k36 as5sp512k36 rev. 3.0 10/13 micross components r eserves the right to change products or speci cations without notice. 3 micross components as5sp512k36 synchronous sram is manufactured to support today?s high performance platforms utilizing the industry?s leading processor elements including those of intel and motorola. the as5sp512k36 supports synchronous sram read and write operations as well as synchronous burst read/write operations. all inputs with the exception of oe\, mode and zz are synchronous in nature and registered on the rising edge of input clock (clk). the type, start and duration of burst mode operations is controlled by mode, adsc\, adsp\ and adv\. all synchronous accesses, including the burst accesses, are enabled via the use of the multiple enable pins, and wait state insertion is supported and controlled via the use of the address advance (adv\). the as5sp512k36 supports both interleaved and linear burst modes. the as5sp512k36 supports byte write operations via the byte write enable (bwe\) and the byte write select pin(s) (bwa\, bwb\, bwc\, bwd\). global writes are supported via the global write enable (gw\). global write enable will override the byte write inputs and will perform a write to all 36 data bits. the as5sp512k36 provides ease of producing very dense arrays via the multiple chip enable input pins and asynchronous output enable. single cycle access operations a single read operation is initiated at the rising edge of clock when all of the following conditions are satis ed: [1] adsp\ or adsc\ is asserted low, [2] chip enables are all asserted active, and [3] the write signals (gw\, bwe\) are high. adsp\ is ignored if ce1\ is high. the address presented to the address inputs is stored within the address registers and address counter/advancement logic and presented to the array core. the corresponding data of the addressed location is propagated to the output registers and passed to the data bus on the next rising clock via the output buffers. the time at which the data is presented to the data bus is as speci ed by either the clock to data valid speci cation or the output enable to data valid spec for the device speed grade chosen. the only exception occurs when the device is emerging from a deselected to selected state where its outputs are tristated in the rst machine cycle and controlled by its output enable (oe\) on following cycle. consecutive single cycle reads are supported. once the sram is deselected by use of the chip enable(s) and either adsp\ or adsc\, its outputs will tri-state immediately. a single adsp\ controlled write operation is initiated when both of the following conditions are satis ed at the rising edge of clock: [1] adsp\ is asserted low, and [2] chip enable(s) are asserted active. the write controls: global write, byte write enable (gw\, bwe\) the individual byte writes (bwa\, bwb\, bwc\, bwd\), and adv\ are ignored on the rst machine cycle. adsp\ triggered write accesses require two (2) machine cycles to complete. if global write is asserted low on the second clock (clk) rise, data will be written into the selected address location. if gw\ is high (inactive) then the write operation is controlled by bwe\ and one or more of the byte write controls (bwa\, bwb\, bwc\ and bwd\). all writes that are initiated in this device are internally self timed. a single adsc\ controlled write operation is initiated at the rising edge of clock when the following conditions are satis ed: [1] adsc\ is asserted low, [2] adsp\ is de-asserted (high), [3] chip enable(s) are asserted (true or active), and [4] the appropriate combination of the write inputs (gw\, bwe\, bwx\) are asserted (active). adsc\ triggered write accesses require a single clock (clk) machine cycle to complete. the adv\ pin is ignored during this cycle. deep power-down mode (sleep) the as5sp512k36 has a deep power-down mode and is controlled by the asynchronous zz pin. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. for the device to be placed successfully into this operational mode the device must be deselected and the chip enables, adsp\ and adsc\ remain inactive for the duration of tzzrec after the zz input returns low. accesses pending when entering ?sleep? mode are not considered valid. functional description
ssram as5sp512k36 as5sp512k36 rev. 3.0 10/13 micross components r eserves the right to change products or speci cations without notice. 4 synchronous truth table (1, 2) ce1\ ce2 ce3\ adsp \ a dsc \ a dv \ wt / rd cl k address accesse d operatio n h x x x l x x na not selected l l x l x x x na not selected l x h l x x x na not selected l l x h l x x na not selected l x h h l x x na not selected l h l l x x x external address begin burst, read l h l h l x wt external address begin burst, write l h l h l x rd external address begin burst, read x x x h h l rd next address continue burst, read h x x x h l rd next address continue burst, read x x x h h l wt next address continue burst, write h x x x h l wt next address continue burst, write x x x h h h rd current address suspend burst, read h x x x h h rd current address suspend burst, read x x x h h h wt current addres s suspend burst, writ e h x x x h h wt current address suspend burst, write notes: 1. x = don?t care 2. wt= write operation in write table, rd= read operation in write table burst sequence tables interleaved burs t burst control state case 1 case 2 case 3 case 4 pin [mode] high a1 a0 a1 a0 a1 a0 a1 a0 first address 00011011 01001110 10110001 fourth address 11100100 linear burst burst control state case 1 case 2 case 3 case 4 pin [mode] low a1 a0 a1 a0 a1 a0 a1 a0 first address 00011011 01101100 10110001 fourth address 11000110 capacitance paramete r symbol max. units input capacitance ci 6pf input/output capacitance cio 8pf write table gw \ bw \ bwa \ bwb \ bwc \ bwd \ operation hhxxxx read hlhhhh read h l l h h h write byte [a] h l h l h h write byte [b] h l h h l l write byte [c], [d] hlllll write all bytes lxxxxx write all bytes asynchronous truth table operation zz oe\ i/o status power-down (sleep) h x high-z read l l dq l h high-z write l x din, high-z de-selected l x high-z absolute maximum ratings* absolute maximum ratings parameter symbol min. max. units voltage on vdd pin vdd -0.3 4.6 v voltage on vddq pins v ddq vdd v voltage on input pins v in -0.3 vdd+0.3 v voltage on i/o pins v io -0.3 vddq+0.3 v power dissipation pd 1.6 w storage temperature tstg -65 150 r c operating temperatures / it -40 85 r c [screening levels] / et -40 105 r c / xt -55 125 r c *stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this speci cation is not implied. exposure to absolute maximum conditions for any duration or segment of time may affect device reliability. ac test loads figure 1 figure 2 r= 1538 ohm@2.5v r= 351 ohm@3.3v 3.3/2.5v output diagram [b] 5 pf r= 317 ohm@3.3v r= 1667 ohm@2.5v output zo=50 ohm 30 pf rt = 50 ohm vt= termination voltage rt= termination resistor vt= 1.50v for 3.3v vddq vt= 1.25v for 2.5v vddq diagram [a]
ssram as5sp512k36 as5sp512k36 rev. 3.0 10/13 micross components r eserves the right to change products or speci cations without notice. 5 dc electrical characteristics (vdd = 3.3v 5%, vddq = 3.3v/2.5v 5%, vddq vdd) [1, 2] ta=min. and max temperatures of screening level chosen symbol parameter test conditions min max units notes vdd power supply voltage 3.465 3.630 v v dd q i/o supply voltage 2.375 vdd v 4 v oh output high voltage vdd=min., ioh=-4ma 3.3v 2.4 v vdd=min., ioh=-1ma 2.5v 2 v v ol output low voltage vdd=min., iol=8ma 3.3v 0.4 v vdd=min., iol=1ma 2.5v 0.4 v v ih input high voltage 3.3v 2 v 2.5v 1.7 v v il input low voltage 3.3v 0.8 v 2.5v 0.7 v iil vdd=max., vin=vss to vdd -5 5 ua 3 iz input leakage, zz pin -30 30 ua 3 iol output leakage output disabled, vout=vssq to vddq -5 5 ua idd operating current vdd=max., f=max., 5.0ns cycle, 200 mhz 475 ma ioh=0ma 6.0ns cycle, 166 mhz 425 ma 7.5ns cycle, 133 mhz 375 ma isb1 automatic ce, power down max vdd, de-selected, current - ttl inputs vin>=vih or vin/=vddq-0.3v 200 ma f=1/tcyc input leakage (except zz) mode pin thermal resistance parameter description test conditions dq package dqc package unit : ja thermal resistance (junction to ambient) 28.66 30.2 o c/w : jc thermal resistance (junction to case) 4.08 6.5 o c/w test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51 notes: [1] [2] [3] [4] vddq should never exceed vdd, vdd and vddq can be connected together overshoot: vih(ac) < vdd +1.5v (pulsewidth less than tcyc/2) undershoot: vil(ac) > -2v (pulsewidth less than tcyclz) mode and zz pins have internal pull-up resistors tpower-up: assumes a linear amp from ov to vdd(min) within zooms. during this time vih ? vdd and vddq ? vdd all voltages referenced to vss (logic ground)
ssram as5sp512k36 as5sp512k36 rev. 3.0 10/13 micross components r eserves the right to change products or speci cations without notice. 6 ac switching characteristics (vdd = 3.3v 5%, vddq = 3.3v/2.5v 5%, vddq vdd) [1] ta=min. and max temperatures of screening level chosen -30 [200mhz] -35 [166mhz] -40 [133mhz] parameter symbol min. max. min. max. min. max. units notes clock (clk) cycle time tcyc 5.00 - 6.00 - 7.50 - ns clock (clk) high time tch 2.00 - 2.20 - 2.50 - ns clock (clk) low time tcl 2.00 - 2.20 - 2.50 - ns clock access time tcd 3.10 3.50 4.00 ns clock (clk) high to output low-z tclz 1.00 - 1.00 - 1.00 - ns 2,3 clock high to output high-z tch z 1.25 3.00 1.25 3.50 1.25 3.50 ns 2,3 output enable to data valid toe - 3.10 - 3.50 - 4.00 ns output hold from clock high toh 1.25 - 1.25 - 1.25 - ns output enable low to output low-z toelz 0.00 - 0.00 - 0.00 - ns 2,3 output enable high to output high-z toehz - 3.00 - 3.50 - 3.50 ns 2,3 address set-up to clk high tas 1.40 1.50 1.50 ns address hold from clk high tah 0.40 0.50 0.50 ns address status set-up to clk high tass 1.40 1.50 1.50 ns address status hold from clk high tash 0.40 0.50 0.50 ns address advance set-up to clk high tadvs 1.40 1.50 1.50 ns address advance hold from clk high tadvh 0.40 0.50 0.50 ns chip enable set-up to clk high (cex\, ce2) tces 1.40 1.50 1.50 ns chip enable hold from clk high (cex\, ce2) tceh 0.40 0.50 0.50 ns data set-up to clk high tds 1.40 1.50 1.50 ns data hold from clk high tdh 0.40 0.50 0.50 ns write set-up to clk high (gw\, bwe\, bwx\) twes 1.40 1.50 1.50 ns write hold from clk high (gw\, bwe\, bwx\) tweh 0.40 0.50 0.50 ns zz high to power down tpd 2 2 2 cycles zz low to power up tpu 2 2 2 cycles notes to switching specifications: 1. configuration signal mode is static and must not change during normal operation. 2. guaranteed but not 100% tested. this parameter is periodically sampled. 3. tested with load in figure 2.
ssram as5sp512k36 as5sp512k36 rev. 3.0 10/13 micross components r eserves the right to change products or speci cations without notice. 7 ac switching waveforms write cycle timing clk adsp\ adsc\ adv\ ax gw\ bwe\, bwx\ ce1\ ce2 ce3\ oe\ dqx,dqpx w1 w2a w2b w2d w2c w3 don't care undefined single write burst write pipelined write tcyc tch tcl tash tass adsp\ ignored with ce1\ inactive tash tass tadvs tadvh adv\ must be inactive for adsp\ write adsc\ initiated write tas tah twes tweh tweh twes tces tceh ce1\ masks adsp\ tds tdh a3 a2 a1
ssram as5sp512k36 as5sp512k36 rev. 3.0 10/13 micross components r eserves the right to change products or speci cations without notice. 8 ac switching waveforms read cycle timing tceh ce1\ masks adsp\ d a e r t s r u b d a e r e l g n i s pipelined read tcyc tch tcl tash adsp\ ignored with ce1\ inactive a1 a2 a3 tadvs tadvh suspend burst adsc\ initiated read tah tweh tas twes unselected with ce2 toe toehz tcd toh tces r1 r2a r2b r2c r2d r3a clk adsp\ adsc\ adv\ ax gw\ bwe\, bwx\ ce1\ ce2 ce3\ oe\ dqx,dqpx undefined don't care tass
ssram as5sp512k36 as5sp512k36 rev. 3.0 10/13 micross components r eserves the right to change products or speci cations without notice. 9 ac switching waveforms read/write cycle timing clk adsp\ adsc\ adv\ ax gw\ bwe\, bwx\ ce1\ ce2 ce3\ oe\ dqx,dqpx r 5 a r 4 a w 3 a w 2 a r 1 a a1o a2i a3i a4o a4o a4o a4o [a] [b] [c] [d] burst read single cycle deselected pipedlined read tcyc tch tcl tass tash tadvs tadvh tah tas twes tweh tces tceh ce1\ unselected i/o disabled within 1 clock cycle after deselect tceh tces toe toehz toelz tcd toh tchz undefined don't care
ssram as5sp512k36 as5sp512k36 rev. 3.0 10/13 micross components r eserves the right to change products or speci cations without notice. 10 power down (sleep mode) the device is placed in this sleep mode via the use of the zz pin, an asynchronous control pin which when asserted, places the array into the lower power or power down mode. awakening the array or leaving the power down (sleep) mode is done so by de-asserting the zz pin . while in the power down or snooze mode, data integrity is guaranteed. accesses pending when the device entered the mode are not considered valid nor is the completion of the operation guaranteed. the device must be de-selected prior to entering the p ower down mode, all chip enables, adsp\ and adsc\ must remain inactive for the duration of zz recovery time (tzzrec). zz mode electrical characteristics zz mode timing diagram [1, 2] ordering information tqfp tcd clock (ns) (mhz) as5sp512k36dq-30/i t 512kx36, 3.3vcore/3.3,2.5vio 3.1 200 as5sp512k36dq-35/i t 512kx36, 3.3vcore/3.3,2.5vio 3.5 166 as5sp512k36dq-40/i t 512kx36, 3.3vcore/3.3,2.5vio 4.0 133 as5sp512k36dq-30/e t 512kx36, 3.3vcore/3.3,2.5vio 3.1 200 as5sp512k36dq-35/e t 512kx36, 3.3vcore/3.3,2.5vio 3.5 166 as5sp512k36dq-40/e t 512kx36, 3.3vcore/3.3,2.5vio 4.0 133 as5sp512k36dq-35/x t 512kx36, 3.3vcore/3.3,2.5vio 3.5 166 as5sp512k36dq-40/x t 512kx36, 3.3vcore/3.3,2.5vio 4.0 133 device number configuration paramete r symbol test conditon min. max. units power down (snooze) mode iddzz zz >/- vdd - 0.2v 165 ma zz active (signal high) to power down tzzs zz >/- vdd - 0.2v 2 tcyc ns zz inactive (signal low) to power up tzzr zz ssram as5sp512k36 as5sp512k36 rev. 3.0 10/13 micross components r eserves the right to change products or speci cations without notice. 11 100-pin tqfp (package designator dq) mechanical definition
ssram as5sp512k36 as5sp512k36 rev. 3.0 10/13 micross components r eserves the right to change products or speci cations without notice. 12 document title plastic encapsulated microcircuit , 18mb, 512k x 36, synchronous sram pipeline burst, single cycle deselect revision history rev # history release date status 2.5 updated max ratings & dc september 2008 release electrical characteristics 2.6 updated micross information october 2010 release 2.7 changed adv\ description text from november 2010 release high to low on page 2, edited adv\ write cycle timing drawing on page 7 2.8 added copper lead frame and rohs may 2011 release compliant options, updated iddzz, pg 10 from 35ma to 165ma, updated logic block diagram on page 2. changed t clz min from 1.25ns to 1.0ns. corrected -30 t oh from 1.65ns to 1.25ns. changed: spec device from to i dd 5ns cycle 350 475 ma 6ns cycle 300 425 ma 7.5ns cycle 275 375 ma i sb1 5ns cycle 160 250 ma 6ns cycle 150 225 ma 7.5ns cycle 140 200 ma i sb2 all 70 200 ma i sb3 all 80 250 ma deleted i sb4 speci cation 2.9 added thermal resistance for dqc september 2011 release package, page 5. 3.0 removed cu-lead frame option october 2013 release

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